CPC H04W 72/02 (2013.01) [H04L 1/08 (2013.01); H04W 72/0453 (2013.01); H04W 72/20 (2023.01)] | 12 Claims |
1. A user equipment (UE), comprising a memory and one or more processors configured to, when executing instructions stored in the memory, cause the UE to:
generate sidelink control information (SCI) stage 2 for transmitting a transport block (TB) to a second UE;
determine a SCI stage 2 scrambling initialization value (Cinit) based on at least a portion of a physical sidelink control channel (PSCCH) cyclic redundancy check (CRC) code and a resource pool constant NCONST RP of A bits, wherein NCONST RP is configured for a resource pool allocated for sidelink communication by the UE and A is an integer between 0 and 31;
generate a scrambling sequence based on the SCI stage 2 Cinit;
transmit the SCI stage 2 to the second UE based on the scrambling sequence.
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