US 12,082,133 B2
Aligning paging occasions and synchronization signal blocks
Peter Pui Lok Ang, San Diego, CA (US); Alexei Yurievitch Gorokhov, San Diego, CA (US); Hari Sankar, San Diego, CA (US); Jafar Mohseni, San Diego, CA (US); Huilin Xu, Temecula, CA (US); Linhai He, San Diego, CA (US); Miguel Griot, La Jolla, CA (US); Peter Gaal, San Diego, CA (US); and Carsten Aagaard Pedersen, Bolton, MA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 10, 2021, as Appl. No. 17/447,328.
Prior Publication US 2023/0081031 A1, Mar. 16, 2023
Int. Cl. H04W 56/00 (2009.01); H04W 8/02 (2009.01); H04W 76/28 (2018.01)
CPC H04W 56/001 (2013.01) [H04W 8/02 (2013.01); H04W 76/28 (2018.02)] 30 Claims
OG exemplary drawing
 
1. A device for wireless communication, comprising:
one or more memories; and
one or more processors, coupled to the one or more memories, configured to:
receive, from a user equipment (UE), a communication associated with a request for an identifier associated with the UE; and
transmit, to the UE, the identifier associated with the UE,
wherein the identifier associated with the UE is based at least in part on a synchronization signal block (SSB) periodicity and a number of paging frames per discontinuous reception (DRX) cycle.