US 12,081,893 B2
Image sensor having multiple vertical signal lines per column in multiple laminated wiring layers
Takafumi Morikawa, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/250,240
Filed by C/O SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed May 14, 2019, PCT No. PCT/JP2019/019102
§ 371(c)(1), (2) Date Dec. 21, 2020,
PCT Pub. No. WO2020/003783, PCT Pub. Date Jan. 2, 2020.
Claims priority of application No. 2018-124044 (JP), filed on Jun. 29, 2018.
Prior Publication US 2021/0127081 A1, Apr. 29, 2021
Int. Cl. H04N 25/78 (2023.01); H01L 27/146 (2006.01)
CPC H04N 25/78 (2023.01) [H01L 27/14636 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a pixel array unit that includes a plurality of pixels in a matrix;
multiple vertical signal lines in a plurality of pixel column units; and
multiple wiring layers on a pixel of the plurality of pixels, wherein
specific wiring layers of the multiple wiring layers include a respective vertical signal line of the multiple vertical signal lines,
orthogonal projections of at least two vertical signal lines of the multiple vertical signal lines on the multiple wiring layers overlap,
a first wiring layer of the multiple wiring layers includes a connection portion to connect a first vertical signal line of the multiple vertical signal lines and the pixel,
the first vertical signal line is in a second wiring layer of the multiple wiring layers,
the connection portion includes a via and a relay line,
the relay line extends in a direction orthogonal to a direction in which the first vertical signal line extends,
the first wiring layer is configured to establish connection with the first vertical signal line in the second wiring layer,
the second wiring layer is one of upper or lower to the first wiring layer,
the second wiring layer is adjacent to the first wiring layer, and
the first vertical signal line is configured to output a pixel signal through the via and the relay line.