US 12,081,891 B2
Solid state imaging element and imaging device to reduce circuit area of a pixel
Futa Mochizuki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/786,046
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Dec. 14, 2020, PCT No. PCT/JP2020/046464
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2021/131831, PCT Pub. Date Jul. 1, 2021.
Claims priority of application No. 2019-234168 (JP), filed on Dec. 25, 2019.
Prior Publication US 2023/0016407 A1, Jan. 19, 2023
Int. Cl. H04N 25/778 (2023.01); H01L 27/146 (2006.01); H04N 25/766 (2023.01)
CPC H04N 25/778 (2023.01) [H01L 27/14612 (2013.01); H04N 25/766 (2023.01)] 10 Claims
OG exemplary drawing
 
1. A solid state imaging element, comprising:
a driving circuit configured to supply a specific reference signal, wherein a level of the specific reference signal gradually fluctuates with lapse of time; and
a plurality of pixels, wherein each of the plurality of pixels includes:
a change amount acquisition section;
an auto-zero transistor configured to initialize the change amount acquisition section to obtain a brightness change amount;
a logarithm response section configured to obtain a logarithm value of a photoelectric current;
a differentiation circuit configured to differentiate the logarithm value and output the differentiated logarithm value as a differentiated signal;
a comparison circuit configured to compare the differentiated signal with a specific threshold; and
a reset control section configured to switch, based on occurrence of a specific address event, the auto-zero transistor by use of the specific reference signal.