CPC H04N 25/59 (2023.01) [H04N 3/155 (2013.01); H04N 23/73 (2023.01); H04N 23/741 (2023.01); H04N 25/53 (2023.01); H04N 25/533 (2023.01); H04N 25/581 (2023.01); H04N 25/583 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01)] | 19 Claims |
1. An imaging element comprising
a plurality of semiconductor substrates stacked on each other, wherein
the plurality of semiconductor substrates include
a first photoelectric converting section that converts light into charges,
a second photoelectric converting section that converts light into charges, the second photoelectric converting section and the first photoelectric converting section being arranged side-by-side in a first direction,
a third photoelectric converting section that converts light into charges, the third photoelectric converting section and the first photoelectric converting section being arranged side-by-side in a second direction that intersects with the first direction,
a first computational circuit that performs a computational process using a first signal based on a charge converted by the first photoelectric converting section,
a second computational circuit that performs a computational process using a second signal based on a charge converted by the second photoelectric converting section,
a third computational circuit that performs a computational process using a third signal based on a charge converted by the third photoelectric converting section, and
a drive control section that performs a control such that
(i) the computational process performed in the first computational circuit is different from the computational process performed in at least one of the second computational circuit and the third computational circuit,
(ii) the computational process performed in the second computational circuit is different from the computational process performed in at least one of the first computational circuit and the third computational circuit, or
(iii) the computational process performed in the third computational circuit is different from the computational process performed in at least one of the first computational circuit and the second computational circuit, and wherein
the plurality of semiconductor substrates further include
a first converting section that converts the first signal into a first digital signal,
a second converting section that converts the second signal into a second digital signal, and
a third converting section that converts the third signal into a third digital signal,
the first computational circuit performs an integration process using the first digital signal,
the second computational circuit performs an integration process using the second digital signal, and
the third computational circuit performs an integration process using the third digital signal.
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