US 12,081,761 B2
Image processing apparatus and method
Atsushi Yamato, Kanagawa (JP); and Takeshi Tsukuba, Tokyo (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Appl. No. 17/424,184
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed Feb. 6, 2020, PCT No. PCT/JP2020/004559
§ 371(c)(1), (2) Date Jul. 20, 2021,
PCT Pub. No. WO2020/162540, PCT Pub. Date Aug. 13, 2020.
Claims priority of provisional application 62/802,477, filed on Feb. 7, 2019.
Prior Publication US 2022/0124334 A1, Apr. 21, 2022
Int. Cl. H04N 19/13 (2014.01); H04N 19/149 (2014.01); H04N 19/176 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/13 (2014.11) [H04N 19/149 (2014.11); H04N 19/176 (2014.11); H04N 19/70 (2014.11)] 20 Claims
OG exemplary drawing
 
1. An image processing apparatus comprising:
circuitry configured to
set an upper limit value of a number of context-coded bins that can be allocated to a processing target block, comprising a plurality of sub-blocks, on a basis of a size of the processing target block and a number of context-coded bins per sub-block;
process a sub-block of the processing target block;
in a case that a current number of the context-coded bins is less than or equal to the upper limit value, derive syntax element values for some levels of transform coefficients by context encoding and derive remaining syntax elements by bypass encoding; and
in a case that the current number of the context-coded bins is greater than the upper limit value, derive the syntax elements for the levels of the transform coefficients by bypass encoding.