CPC H04N 19/117 (2014.11) [H04N 19/105 (2014.11); H04N 19/46 (2014.11); H04N 19/80 (2014.11)] | 13 Claims |
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
executes (i) a first process of applying a first filter to a first image to generate a second image, holding the second image as a reference image, and displaying the second image, and (ii) a second process of applying a second filter to the first image to generate the second image, not holding the second image as a reference image, holding the first image as a reference image, and displaying the second image;
writes coefficients of each of one or more filter candidates that are candidates for the second filter into a bitstream, the coefficients being included in a first storage location when written into the bitstream; and
writes a parameter that specifies, for each image, one of the one or more filter candidates as the second filter into the bitstream, the parameter being included in a second storage location when written into the bitstream, the second storage location being different from the first storage location.
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