CPC H04N 19/117 (2014.11) [H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/82 (2014.11)] | 19 Claims |
1. An image processing device comprising:
a decoding circuit that decodes a bitstream to generate a decoded image in accordance with a block structure having a hierarchical structure in which a transform block, a prediction block, and a coding block are unified;
a filter circuit that applies a deblocking filter to pixels of a line orthogonal to a sub-block boundary that is a boundary between sub-blocks obtained by dividing the transform block of the decoded image generated by the decoding circuit; and
a decision circuit that decides whether or not the deblocking filter is applied, depending on a block size of the sub-block, wherein
in response to the block size of the sub-block of the line orthogonal to the sub-block boundary between the sub-blocks being less a predetermined size, the deblocking filter is not applied, and
in response to the block size of the sub-block of the line orthogonal to the sub-block boundary between the sub-blocks being equal to or greater than the predetermined size, the deblocking filter is applied, the filter circuit determines the deblocking filter in accordance with the block size of the sub-block of the line orthogonal to the sub-block boundary between the sub-blocks such that application target pixels to which the deblocking filter is applied at one sub-block boundary do not include a pixel referred to in application of the deblocking filter at another sub-block boundary and applies the determined deblocking filter to the pixels of the line orthogonal to the sub-block boundary between the sub-blocks.
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