CPC H04N 17/00 (2013.01) [G06F 11/08 (2013.01); H04N 5/147 (2013.01)] | 6 Claims |
1. A video signal processing device, comprising:
a selection/output unit that receives a video signal including a sequence of a plurality of pixel data pieces over a plurality of frames, and that sequentially selects and outputs sequences of image data pieces of first to kth split image regions (k being an integer of 2 or greater) that are respectively at same positions over the plurality of frames;
a CRC calculation circuit that executes a cyclic redundancy check (CRC) calculation on the sequence of the plurality of pixel data pieces received by the selection/output unit;
a calculation result sorting unit that generates first to kth test values corresponding, respectively, to the first to kth split image regions based on a calculation result of the CRC calculation circuit;
a freeze determination unit that, based on the first to kth test values corresponding to one frame of the video signal and the first to kth test values corresponding to another frame, determines whether a change has occurred in video of the first to kth split image regions between the plurality of frames, and generates first to kth freeze determination signals representing respective determination results; and
a video freeze detection unit that, by determining whether or not a state in which no change has occurred in the video is continuing over a prescribed number of frame periods based on the first to kth freeze determination signals, detects whether or not video based on the video signal is frozen.
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