US 12,081,649 B2
Error resilient cryptographic units and methods
Vinodh Gopal, Westborough, MA (US); and Kirk Yap, Westborough, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 2, 2020, as Appl. No. 17/010,577.
Prior Publication US 2020/0403779 A1, Dec. 24, 2020
Int. Cl. G06F 21/64 (2013.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); H04L 9/06 (2006.01); H04L 9/32 (2006.01)
CPC H04L 9/0643 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1004 (2013.01); G06F 11/1044 (2013.01); H04L 9/0637 (2013.01); H04L 9/3242 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an encryption circuitry to receive unencrypted data, the encryption circuitry to encrypt the unencrypted data to generate encrypted data;
first circuitry coupled with the encryption circuitry, the first circuitry to:
generate a first checksum for a copy of the unencrypted data;
generate a second checksum for a copy of the encrypted data; and
combine the first and second checksums to generate a first value;
a decryption circuitry to receive the encrypted data, the decryption circuitry to decrypt the encrypted data to generate unencrypted data; and
second circuitry to:
generate a third checksum for a copy of the encrypted data that is decrypted;
generate a fourth checksum for a copy of the unencrypted data that is generated by said decrypting the encrypted data;
combine the third and fourth checksums to generate a second value; and
compare the first value and the second value.