CPC H04L 7/08 (2013.01) [H04L 7/0016 (2013.01); H04L 7/041 (2013.01); H04W 64/003 (2013.01)] | 20 Claims |
1. A transceiver comprising:
a transmit chain;
a receive chain;
self-receive hardware coupling the transmit chain to the receive chain;
a first clock; and
a processor configured to:
generate a first synchronization signal via the transmit chain;
sample a first self-receive signal via self-receive hardware and the receive chain;
calculate a time-of-arrival of the first self-receive signal based on the first clock;
sample a second synchronization signal via the receive chain, the second synchronization signal transmitted by a second transceiver;
calculate a time-of-arrival of the second synchronization signal based on the first clock; and
calculate a time bias between the first clock and a second clock of the second transceiver based on the time-of-arrival of the first self-receive signal and the time-of-arrival of the second synchronization signal.
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