US 12,081,428 B2
Method and system for testbench component lock-up identification during simulation
Manickam Muthiah, Shrewsbury, MA (US); Rohit Kumar, Shrewsbury, MA (US); Shashank Nafde, Milpitas, CA (US); and Razi Abdul Rahim, Willowbrook, IL (US)
Assigned to HCL America Inc.
Filed by HCL America Inc., Sunnyvale, CA (US)
Filed on Feb. 18, 2022, as Appl. No. 17/674,895.
Prior Publication US 2023/0269163 A1, Aug. 24, 2023
Int. Cl. H04L 43/50 (2022.01); H04L 12/42 (2006.01); H04L 43/12 (2022.01)
CPC H04L 43/50 (2013.01) [H04L 12/42 (2013.01); H04L 43/12 (2013.01)] 23 Claims
OG exemplary drawing
 
14. A system for identifying locked-up simulation testbench components during a simulation, the system comprising:
a processor; and
a memory coupled to the processor, wherein the memory stores processor executable instructions, which, on execution, causes the processor to:
create, by an initiator simulation testbench component from a plurality of simulation testbench components, at least one migrant packet, wherein the plurality of simulation testbench components are sequentially connected in at least one daisy loop;
circulate, during a component identification cycle, each of the at least one migrant packet in an associated predefined direction through each of the plurality of simulation testbench components in the associated daisy loop from the at least one daisy loop, wherein each of the at least one migrant packet returns to the initiator simulation testbench component at completion of the component identification cycle, and wherein, to circulate, the processor executable instruction further causes the process to:
determine, by each of the at least one migrant packet, at least one attribute associated with each of the plurality of simulation testbench components;
circulate, during an issue identification cycle, each of the at least one migrant packet in the associated predefined direction through each of the plurality of simulation testbench components in the associated daisy loop, wherein, to circulate each of the least one migrant packet, the processor executable instruction further causes the process to:
initiate, by the initiator simulation testbench component, a timer in each of the at least one migrant packet before initiating circulation of the at least one migrant packet;
send, by the initiator simulation testbench component, each of the at least one migrant packet to subsequent simulation testbench components from the plurality of simulation testbench components, wherein each of the at least one migrant packet is passed on in a sequential manner amongst the plurality of simulation testbench components based on the associated daisy loop;
perform, by each of the subsequent simulation testbench components, at least one of:
receive a migrant packet from a preceding simulation testbench component in the associated daisy loop;
reset the timer associated with the migrant packet to a predefined value after reaching an idle state; and
send, the migrant packet, to a subsequent simulation testbench component in the associated daisy loop, in response to resetting the timer; and
identify, by a migrant packet from the at least one migrant packet, a locked-up simulation testbench component from the subsequent simulation testbench components based on the at least one attribute associated with locked-up simulation testbench component, wherein the locked-up simulation testbench component fails to reset the timer associated with the migrant packet.