| CPC H04L 25/03025 (2013.01) [H04L 25/03267 (2013.01); H04L 2025/03777 (2013.01)] | 20 Claims |
|
1. A decision feedback equalizer (DFE), comprising:
a summer configured to receive a signal stream; and
a plurality of feedback taps;
wherein an input node of a first feedback tap of the plurality of feedback taps is coupled to an output node of the summer, and the first feedback tap comprises:
a pre-amplifier configured to be clocked by a first clock signal, wherein the pre-amplifier is configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream;
a combined latch coupled to an output node of the pre-amplifier, wherein the combined latch comprises:
a latch amplifier configured to be clocked by the first clock signal and a second clock signal, wherein both the first clock signal and the second clock signal are configured to be determined by a main clock of the DFE;
a main latch configured to be clocked by the second clock signal; and
a buffer amplifier configured to be clocked by an inverse signal of the second clock signal; and
a digital to analog converter (DAC) coupled to an output node of the combined latch,
wherein the first postcursor is for being provided to the pre-amplifier without being provided to the summer.
|