CPC H04B 17/14 (2015.01) [H04B 17/19 (2015.01)] | 20 Claims |
13. A radio frequency (RF) chip comprising a digital front-end, the digital front-end comprising:
a waveform generator configured to generate at least one M-point inverse fast Fourier transform (IFFT) sample based on a resource block (RB) configuration and a pseudo-random binary sequence (PRBS), where M is a positive integer;
wherein the waveform generator comprises:
N readers, each of the N readers being configured to generate an output IFFT sample based on one of the at least one M-point IFFT sample, wherein each of the generated N output IFFT samples is different from one another, where N is a positive integer;
N frequency shifters, each of the N frequency shifters being configured to shift a central frequency of the output IFFT sample generated by a respective reader of the N readers to separate the central frequencies of the output IFFT samples of the N readers; and
an adder configured to combine the shifted N output IFFT samples to generate an L-point IFFT testing signal, where L is a positive integer greater than M, wherein M×N=L.
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