US 12,081,268 B2
Resistivity engineered substrate for RF common-mode suppression
Long Chen, Marlboro, NJ (US); and Leonard Jan-Peter Ketelsen, Clinton, NJ (US)
Assigned to ACACIA TECHNOLOGY, INC., San Jose, CA (US)
Filed by ACACIA COMMUNICATIONS, INC., Maynard, MA (US)
Filed on Jan. 6, 2023, as Appl. No. 18/094,205.
Application 18/094,205 is a continuation of application No. 16/995,732, filed on Aug. 17, 2020, granted, now 11,552,710.
Prior Publication US 2023/0155683 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01S 5/026 (2006.01); G02B 6/12 (2006.01); G02B 6/13 (2006.01); H04B 10/032 (2013.01); H04B 10/25 (2013.01); H04B 10/50 (2013.01); H04J 14/02 (2006.01)
CPC H04B 10/50 (2013.01) [H04B 10/032 (2013.01); H04B 10/25 (2013.01); H04J 14/0254 (2013.01); G02B 6/12 (2013.01); G02B 6/13 (2013.01); H01S 5/0261 (2013.01); H01S 5/0262 (2013.01); H01S 5/0265 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A photonic integrated circuit (PIC) comprising:
a semiconductor substrate comprising a top portion having a first resistivity and a bottom portion having a second resistivity lower than the first resistivity, the top portion and bottom portion arranged along a vertical direction normal to a surface of the semiconductor substrate;
a conductor disposed above the top portion of the semiconductor substrate and extending in a plane parallel to the surface; and
a photonic component disposed on the semiconductor substrate and coupled to the conductor.