US 12,081,253 B2
Digital self-calibration for automatic offset cancellation
Nunzio Spina, Catania (IT); Giuseppe Palmisano, S. Giovanni la Punta (IT); and Alessandro Castorina, Acireale (IT)
Assigned to STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jul. 14, 2023, as Appl. No. 18/352,424.
Application 18/352,424 is a continuation of application No. 17/457,496, filed on Dec. 3, 2021, granted, now 11,750,234.
Prior Publication US 2023/0361796 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 1/16 (2006.01); H03F 3/19 (2006.01); H03F 3/24 (2006.01); H04L 27/06 (2006.01)
CPC H04B 1/16 (2013.01) [H03F 3/19 (2013.01); H03F 3/245 (2013.01); H04L 27/06 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver circuit comprising:
a first resistor string comprising a first plurality of resistors coupled in series, wherein the first plurality of resistors comprise first resistors and second resistors connected at a first node;
a first transistor and a second transistor coupled in parallel between a first end of the first resistor string and a reference voltage node, wherein a second end of the first resistor string is coupled to a supply voltage node;
a second resistor string comprising a second plurality of resistors coupled in series, wherein the second plurality of resistors comprise third resistors and fourth resistors connected at a second node;
a third transistor coupled between a first end of the second resistor string and the reference voltage node, wherein a second end of the second resistor string is coupled to the supply voltage node;
a plurality of switches coupled in parallel, wherein each switch of the plurality of switches is coupled between a third node and a respective node in the second resistor string; and
an amplifier, wherein a first input terminal of the amplifier is coupled to the first node, and a second input terminal of the amplifier is coupled to the third node.