an error correction code (ECC) logic circuit configured to generate write data and write parity from write input data when a write operation in an operation mode is performed, and generate converted data from read data and read parity when a read operation in the operation mode is performed;

a global buffer configured to store buffer data; and

a multiplication and accumulation (MAC) operator configured to receive the buffer data from the global buffer through a data line and receive the converted da ta fromthe ECC logic circuit to perform a MAC arithmetic operation with the converted data and the buffer data to generate MAC operation result data,

wherein the ECC logic circuit removes one or more bits included in the write input data and generates the write data, based on the remaining bits when the write operation in the operation mode is performed.