US 12,081,234 B2
ECC memory chip encoder and decoder
Kjersten E. Criss, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 26, 2022, as Appl. No. 17/874,212.
Application 17/874,212 is a continuation of application No. 16/905,384, filed on Jun. 18, 2020, granted, now 11,601,137.
Prior Publication US 2023/0049851 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/19 (2006.01); H03M 13/29 (2006.01)
CPC H03M 13/1105 (2013.01) [H03M 13/19 (2013.01); H03M 13/2942 (2013.01); H03M 13/617 (2013.01); H03M 13/00 (2013.01); H03M 13/11 (2013.01); H03M 13/29 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory device comprising:
error correction code (ECC) encoder logic circuitry; and
ECC decoder logic circuitry to:
read a code word from memory, the code word including data bits and ECC check bits, wherein the data bits are divided into data blocks, and
in response to a multi-bit error limited to one of the data blocks, use an ECC code to insert mis-corrections of the multi-bit error to the code word, where, the ECC code provides for first and second error correction schemes, where the first error correction scheme inserts mis-corrections within the data block with the multi-bit error, and where, the second error correction scheme inserts mis-corrections within the ECC check bits.