US 12,081,229 B2
Common-mode current removal schemes for digital-to-analog converters
Sumant Ramprasad, Cupertino, CA (US); Nitz Saputra, Burlingame, CA (US); and Ashok Swaminathan, Cardiff, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 11, 2022, as Appl. No. 17/811,706.
Prior Publication US 2024/0014824 A1, Jan. 11, 2024
Int. Cl. H03M 1/08 (2006.01); H03M 1/74 (2006.01); H03M 1/78 (2006.01)
CPC H03M 1/08 (2013.01) [H03M 1/742 (2013.01); H03M 1/785 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A digital-to-analog converter (DAC) circuit comprising:
a plurality of current-steering cells;
a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches; and
an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit, wherein the adjustable resistance circuit comprises a switched network of resistive elements.