US 12,081,224 B2
Method for communicating a reference time base in a microcontroller, and corresponding microcontroller integrated circuit
Laurent Meunier, Coulaines (FR); and Vincent Pascal Onde, Fuveau (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Grand Ouest) SAS, Le Mans (FR)
Filed on Jun. 17, 2022, as Appl. No. 17/807,452.
Claims priority of application No. 2107062 (FR), filed on Jun. 30, 2021.
Prior Publication US 2023/0006684 A1, Jan. 5, 2023
Int. Cl. G06F 7/24 (2006.01); G06F 1/14 (2006.01); G06F 9/48 (2006.01); H03L 7/099 (2006.01); H03L 7/24 (2006.01)
CPC H03L 7/24 (2013.01) [G06F 1/14 (2013.01); G06F 9/4812 (2013.01); H03L 7/0992 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for communicating a value of a reference time base stored in a counter register accessible by a central processing unit (CPU), the method comprising:
generating a low-frequency clock signal, having a first frequency, in a standby mode and in a run mode of the CPU;
generating a high-frequency clock signal, having a second frequency higher than the first frequency, in the run mode;
updating the value of the reference time base at each period of the low-frequency clock signal in the standby mode; and
accessing the counter register with the high-frequency clock signal in the run mode,
wherein a value of the reference time base stored in a root counter register is updated at each period of the low-frequency clock signal in the standby mode and in the run mode, and
wherein the value of the reference time base stored in the counter register is synchronized to the value of the reference time base of the root counter register at each period of the low-frequency clock signal in the run mode.