US 12,081,218 B2
Multiphase digital frequency synthesizer with fractional division
Ravi Kumar, Noida (IN); Gaurav Agrawal, Noida (IN); Deependra Kumar Jain, Noida (IN); and Krishna Thakur, GautamBudh Nagar (IN)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Apr. 6, 2023, as Appl. No. 18/296,518.
Claims priority of application No. 202211052246 (IN), filed on Sep. 13, 2022.
Prior Publication US 2024/0088879 A1, Mar. 14, 2024
Int. Cl. H03K 3/03 (2006.01); H03K 3/017 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01)
CPC H03K 5/00006 (2013.01) [H03K 3/017 (2013.01); H03K 3/0315 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multiphase digital frequency synthesizer, comprising:
a multiphase ring oscillator that is configured to provide a plurality of phased clock signals;
a clock divider that is configured to divide a selected one of the plurality phased clock signals by an integer value and a carry value and that provides a divided clock signal;
positive select circuitry that accumulates a positive select value with a fractional division factor for providing a first accumulated value, that performs a modulo function on the first accumulated value for providing a first modulo value, and that updates the positive select value in successive cycles of the divided clock signal using the first modulo value;
carry circuitry that determines the carry value by dividing the first modulo value by a number of the phased clock signals and that updates the carry value in successive cycles of the divided clock signal;
positive multiplex circuitry that selects from among the plurality of phased clock signals using the positive select value for providing a positive multiplexed clock signal; and
fractional phase addition circuitry that provides a first output clock signal based on a selected one of the plurality of phased clock signals, the divided clock signal, and the positive multiplexed clock signal.