US 12,081,211 B2
High power positive logic switch
Payman Shanjani, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Oct. 12, 2022, as Appl. No. 17/964,524.
Application 17/964,524 is a continuation of application No. 17/141,706, filed on Jan. 5, 2021, granted, now 11,476,849.
Claims priority of provisional application 62/957,705, filed on Jan. 6, 2020.
Prior Publication US 2023/0112755 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/687 (2006.01); H03K 19/017 (2006.01)
CPC H03K 17/6872 (2013.01) [H03K 19/017 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A circuit including:
(a) a set of one or more field-effect transistor (FET) switches coupled in series, the set having a first end and a second end, wherein at least one FET switch of the set of FET switches requires a relatively negative Vas to turn OFF and is configured so as to not require a negative voltage;
(b) a first end-cap FET having a gate, a first terminal coupled in series with the first end of the set of one or more FET switches, and a second terminal configured to be coupled to a first RF signal source, wherein the first end-cap FET turns OFF when the Vas of the first end-cap FET is essentially zero volts; and
(c) a first switch circuit including a first NMOSFET coupled between the second terminal and the gate of the first end-cap FET.