US 12,081,204 B2
Power switch
Laurent Lopez, Peynier (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Aug. 10, 2022, as Appl. No. 17/885,086.
Claims priority of application No. 2108858 (FR), filed on Aug. 24, 2021.
Prior Publication US 2023/0064471 A1, Mar. 2, 2023
Int. Cl. H03K 17/16 (2006.01)
CPC H03K 17/161 (2013.01) 12 Claims
OG exemplary drawing
 
1. A device, comprising:
a first terminal configured to connect to a first voltage source supplying a first supply potential referenced to ground;
a second terminal configured to supply a second potential referenced to ground;
a third terminal configured to connect to a second voltage source supplying a third supply potential referenced to ground;
a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal;
a second PMOS transistor having a source connected to the second terminal;
a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second PMOS transistor;
a control circuit configured to generate gate control signals for controlling the first, second, and third transistors, the control circuit being configured to receive the first, second, and third supply potentials;
wherein the control circuit comprises:
a first circuit configured to supply a first high reference potential equal to A times the first supply potential and a first low reference potential equal to B times the first supply potential, with A and B positive numbers strictly less than 1, A being greater than B; and
a second circuit configured to supply a second high reference potential equal to C times the second supply potential and a second low reference potential equal to D times the second supply potential, with C and D positive numbers strictly less than 1, C being greater than D.