US 12,081,201 B2
Inrush current suppression circuit
Yuichi Sawahara, Kanagawa (JP); and Hideaki Majima, Tokyo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Mar. 8, 2023, as Appl. No. 18/119,241.
Claims priority of application No. 2022-152171 (JP), filed on Sep. 26, 2022.
Prior Publication US 2024/0106427 A1, Mar. 28, 2024
Int. Cl. H03K 17/081 (2006.01); H03K 17/0812 (2006.01); H03K 17/687 (2006.01); H03K 17/74 (2006.01)
CPC H03K 17/08122 (2013.01) [H03K 17/6871 (2013.01); H03K 17/74 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An inrush current suppression circuit comprising:
a normally-on transistor;
a normally-off transistor connected in series with the normally-on transistor;
a first drive circuit configured to drive the normally-on transistor;
a second drive circuit configured to drive the normally-off transistor;
a diode connected between an output of the first drive circuit and an output terminal of the normally-off transistor;
a first power source smoothing circuit configured to perform smoothing of a source current to be supplied to the first drive circuit and the second drive circuit; and
a switch circuit configured to switch connection/disconnection of a current path passing through the first power source smoothing circuit.