US 12,081,171 B2
Semiconductor device
Yuto Yakubo, Kanagawa (JP); Shoki Miyata, Kanagawa (JP); Akio Suzuki, Kanagawa (JP); and Takayuki Ikeda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Appl. No. 17/923,653
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
PCT Filed May 7, 2021, PCT No. PCT/IB2021/053880
§ 371(c)(1), (2) Date Nov. 7, 2022,
PCT Pub. No. WO2021/229385, PCT Pub. Date Nov. 18, 2021.
Claims priority of application No. 2020-085605 (JP), filed on May 15, 2020.
Prior Publication US 2023/0188094 A1, Jun. 15, 2023
Int. Cl. H03D 7/14 (2006.01); H01L 29/786 (2006.01)
CPC H03D 7/1458 (2013.01) [H01L 29/78648 (2013.01); H01L 29/7869 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a mixer circuit and a bias circuit,
wherein the mixer circuit comprises a voltage-to-current conversion portion, a current switch portion, and a current-to-voltage conversion portion,
wherein the bias circuit comprises a bias supply portion and a first transistor,
wherein the voltage-to-current conversion portion comprises a second transistor and a third transistor,
wherein the bias circuit is configured to output a bias voltage to be supplied to a gate of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor,
wherein the bias circuit comprises a voltage holding portion electrically connected to the bias supply portion, and a buffer portion electrically connected to the voltage holding portion,
wherein an output of the buffer portion is electrically connected to the gate of the second transistor and the gate of the third transistor,
wherein the voltage holding portion is configured to hold the bias voltage, and
wherein the buffer portion is configured to amplify power of the bias voltage.