US 12,080,804 B2
Semiconductor integrated circuit device
Hiroyuki Shimbo, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Yokohama (JP)
Filed on May 10, 2023, as Appl. No. 18/315,317.
Application 18/315,317 is a continuation of application No. 17/674,568, filed on Feb. 17, 2022, granted, now 11,688,814.
Application 17/674,568 is a continuation of application No. 17/125,532, filed on Dec. 17, 2020, granted, now 11,289,610, issued on Mar. 29, 2022.
Application 17/125,532 is a continuation of application No. 16/893,167, filed on Jun. 4, 2020, granted, now 10,903,370, issued on Jan. 26, 2021.
Application 16/893,167 is a continuation of application No. 16/110,661, filed on Aug. 23, 2018, granted, now 10,707,354, issued on Jul. 7, 2020.
Application 16/110,661 is a continuation of application No. PCT/JP2017/005697, filed on Feb. 16, 2017.
Claims priority of application No. 2016-034417 (JP), filed on Feb. 25, 2016.
Prior Publication US 2023/0275160 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); B82Y 10/00 (2011.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/118 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01)
CPC H01L 29/78696 (2013.01) [B82Y 10/00 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/11807 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 21/823807 (2013.01); H01L 21/823871 (2013.01); H01L 29/775 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising
a first standard cell constituting a NAND gate and including first and second p-type nanowire field effect transistors (FETs), and first and second n-type nanowire FETs,
the first and second p-type nanowire FETs are connected together in parallel, and the first and second n-type nanowire FETs are connected together in series,
each of the first and second p-type nanowire FETs and the first and second n-type nanowire FETs including:
a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of nanowires;
first and second pads arranged at both ends of the nanowire in the first direction, and connected to the nanowire; and
a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire, wherein:
the first pad of the first p-type nanowire FET, the first pad of the second p-type nanowire FET, and the second pad of the second p-type nanowire FET are arranged at a first pitch in the first direction,
the first pad of the first n-type nanowire FET, the first pad of the second n-type nanowire FET, and the second pad of the second n-type nanowire FET are arranged at the first pitch in the first direction,
a cell width of the first standard cell that is a dimension of the first standard cell in the first direction is an integral multiplication of the first pitch, and
the gate electrode of the first p-type nanowire FET and the gate electrode of the first n-type nanowire FET are integrally formed with each other as a first gate line extending in the second direction, the gate electrode of the second p-type nanowire FET and the gate electrode of the second n-type nanowire FET are integrally formed with each other as a second gate line extending in the second direction.