US 12,080,802 B2
Semiconductor device comprising silicon and oxide semiconductor in channel formation region
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on May 25, 2023, as Appl. No. 18/201,815.
Application 18/201,815 is a continuation of application No. 17/183,670, filed on Feb. 24, 2021, granted, now 11,710,795.
Application 17/183,670 is a continuation of application No. 16/812,546, filed on Mar. 9, 2020, granted, now 11,133,419, issued on Sep. 28, 2021.
Application 16/812,546 is a continuation of application No. 16/272,287, filed on Feb. 11, 2019, granted, now 10,608,118, issued on Mar. 31, 2020.
Application 16/272,287 is a continuation of application No. 15/882,139, filed on Jan. 29, 2018, granted, now 10,263,120, issued on Apr. 16, 2019.
Application 15/882,139 is a continuation of application No. 14/964,950, filed on Dec. 10, 2015, granted, now 9,887,298, issued on Feb. 6, 2018.
Application 14/964,950 is a continuation of application No. 14/330,597, filed on Jul. 14, 2014, granted, now 9,214,520, issued on Dec. 15, 2015.
Application 14/330,597 is a continuation of application No. 13/684,290, filed on Nov. 23, 2012, granted, now 8,779,420, issued on Jul. 15, 2014.
Application 13/684,290 is a continuation of application No. 12/951,249, filed on Nov. 22, 2010, granted, now 8,748,881, issued on Jun. 10, 2014.
Claims priority of application No. 2009-270857 (JP), filed on Nov. 28, 2009.
Prior Publication US 2023/0299207 A1, Sep. 21, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/22 (2006.01); H01L 29/221 (2006.01); H01L 29/24 (2006.01); H01L 29/26 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/2206 (2013.01); H01L 29/221 (2013.01); H01L 29/24 (2013.01); H01L 29/263 (2013.01); H01L 29/42356 (2013.01); H01L 29/45 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor comprising silicon in a channel formation region; and
a second transistor comprising an oxide semiconductor in a channel formation region,
wherein a first insulating layer is provided over the channel formation region of the first transistor,
wherein a first gate electrode of the first transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the first gate electrode of the first transistor,
wherein a layer comprising the channel formation region of the second transistor is provided over the second insulating layer,
wherein a third insulating layer is provided over the layer comprising the channel formation region of the second transistor,
wherein a second gate electrode of the second transistor is provided over the third insulating layer,
wherein a fourth insulating layer is provided over the second gate electrode of the second transistor,
wherein a fifth insulating layer is provided over the fourth insulating layer,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor via an opening provided in the second insulating layer, an opening provided in the third insulating layer, an opening provided in the fourth insulating layer, and an opening provided in the fifth insulating layer,
wherein the one of the source electrode and the drain electrode of the second transistor has a three-layer structure in which an aluminum layer is stacked over a first titanium layer and a second titanium layer is stacked over the aluminum layer,
wherein the first titanium layer is in contact with the layer comprising the channel formation region of the second transistor,
wherein the oxide semiconductor comprises a crystalline region, and
wherein a third gate electrode of the second transistor overlaps with the channel formation region of the second transistor and the second gate electrode of the second transistor.