| CPC H01L 29/7824 (2013.01) [H01L 29/0649 (2013.01); H01L 29/1079 (2013.01); H01L 29/517 (2013.01); H01L 29/66689 (2013.01)] | 9 Claims |
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1. A manufacturing method of a high voltage semiconductor device, comprising:
providing a semiconductor substrate;
forming an isolation structure, wherein at least a part of the isolation structure is formed in the semiconductor substrate and surrounds a channel region in the semiconductor substrate;
forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer comprises:
a first portion; and
a second portion disposed at two opposite sides of the first portion in a horizontal direction, wherein a thickness of the first portion is greater than a thickness of the second portion;
forming a gate structure on the gate oxide layer and the isolation structure;
performing a first doping process for forming two drift regions in the semiconductor substrate, wherein the two drift regions are located at two opposite sides of the channel region in the horizontal direction respectively, and at least a part of the isolation structure is located in the two drift regions; and
performing a third doping process to the semiconductor substrate before the step of forming the gate oxide layer and after the first doping process, wherein a second treated region comprising second impurities is formed above the two drift regions by the third doping process.
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