| CPC H01L 29/7813 (2013.01) [H01L 27/088 (2013.01); H01L 29/24 (2013.01); H10B 12/30 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
a conductive line on a substrate and extending in a first direction;
a first interlayer insulating layer on the substrate, the first interlayer insulating layer exposing at least a portion of the conductive line and defining a channel trench extending in a second direction that crosses the first direction, the channel trench having a vertical side surface extending from a top to a bottom surface;
a channel layer extending along the bottom surface of the channel trench and along the vertical side surface of the channel trench;
a first gate electrode and a second gate electrode spaced apart from each other in the first direction and extending in the second direction, the first gate electrode and the second gate electrode inside the channel trench;
a first gate insulating layer between the channel layer and the first gate electrode; and
a second gate insulating layer between the channel layer and the second gate electrode,
wherein the channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line, and
the first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.
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