US 12,080,785 B2
Method of controlling wafer bow in a type III-V semiconductor device
Seong-Eun Park, Chandler, AZ (US); Jianwei Wan, Chandler, AZ (US); Mihir Tungare, Gilbert, AZ (US); Peter Kim, Chandler, AZ (US); and Srinivasan Kannan, Chandler, AZ (US)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jul. 11, 2022, as Appl. No. 17/861,913.
Application 17/861,913 is a division of application No. 16/895,585, filed on Jun. 8, 2020, granted, now 11,387,355.
Application 16/895,585 is a division of application No. 15/628,723, filed on Jun. 21, 2017, granted, now 10,720,520, issued on Jul. 21, 2020.
Prior Publication US 2022/0344499 A1, Oct. 27, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/267 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/778 (2013.01) [H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/0242 (2013.01); H01L 21/02458 (2013.01); H01L 21/02505 (2013.01); H01L 21/0254 (2013.01); H01L 29/267 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of forming a type III-V semiconductor device, the method comprising:
providing a type IV semiconductor substrate comprising a main surface;
forming a type III-V semiconductor channel region over the type IV semiconductor substrate, the type III-V semiconductor channel region comprising a two-dimensional carrier gas,
forming a type III-V semiconductor lattice transition region between the type IV semiconductor substrate and the type III-V semiconductor channel region, the type III-V semiconductor lattice transition region being configured to alleviate mechanical stress arising from lattice mismatch between the type IV semiconductor substrate and the type III-V semiconductor channel region,
wherein forming the type III-V semiconductor lattice transition region comprises:
forming a first lattice transition layer over the type IV semiconductor substrate, the first lattice transition layer having a first metallic concentration;
forming a second lattice transition layer directly on the first transition layer, the second lattice transition layer having a second metallic concentration different from the first metallic concentration;
forming a third lattice transition layer directly on the second transition layer, the third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration; and
forming a fourth lattice transition layer directly on the third transition layer, the fourth lattice transition layer having a fourth metallic concentration that is greater than 0 percent and is lower than the first metallic concentration.
 
8. A method of forming a type III-V semiconductor device, the method comprising:
providing a type IV semiconductor substrate comprising a main surface;
forming a type III-V semiconductor lattice transition region over the main surface of the semiconductor substrate; and
forming a type III-V semiconductor channel region over the type III-V semiconductor lattice transition region, the type-III-V semiconductor channel region comprising a two-dimensional carrier gas,
wherein the type III-V semiconductor lattice transition region is electrically inactive and is configured to alleviate lattice mismatch between the type IV semiconductor substrate and the type III-V semiconductor channel region, and
wherein forming the type III-V semiconductor channel region comprises:
forming a first lattice transition layer over the type IV semiconductor substrate, wherein the first lattice transition layer is a layer of AlGaN;
forming a second lattice transition layer directly on the first transition layer, wherein the second lattice transition layer is a layer of AlGaN with a different aluminum content than the first lattice transition layer;
forming a third lattice transition layer directly on the second transition layer, wherein the third lattice transition layer is a layer of AlGaN with a higher aluminum content than the first lattice transition layer; and
forming a fourth lattice transition layer directly on the third transition layer, wherein the fourth lattice transition layer is a layer of AlGaN with a lower aluminum content as the first lattice transition layer.