US 12,080,781 B2
Fabrication of thin film fin transistor structure
Noriyuki Sato, Hillsboro, OR (US); Sarah Atanasov, Beaverton, OR (US); Abhishek A. Sharma, Portland, OR (US); Bernhard Sell, Portland, OR (US); Chieh-Jen Ku, Hillsboro, OR (US); Elliot N. Tan, Portland, OR (US); Hui Jae Yoo, Portland, OR (US); Travis W. Lajoie, Forest Grove, OR (US); Van H. Le, Portland, OR (US); Pei-Hua Wang, Beaverton, OR (US); Jason Peck, Hillsboro, OR (US); and Tobias Brown-Heft, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2020, as Appl. No. 17/129,867.
Prior Publication US 2022/0199807 A1, Jun. 23, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0924 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of forming a fin transistor structure, comprising:
patterning a plurality of backbone pillars on a semiconductor substrate;
conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate; and
performing a spacer etch of the spacer layer to leave a first sidewall and a second sidewall of the spacer layer on a backbone pillar to form a first fin and a second fin, respectively, of the fin transistor structure, wherein the first fin has a first side higher than a second side, and the second fin has a first side higher than a second side, and wherein the first side of the first fin faces toward the first side of the second fin.