US 12,080,779 B2
Capping layer for gate electrodes
Chin-Hsiang Lin, Hsinchu (TW); Teng-Chun Tsai, Hsinchu (TW); Huang-Lin Chao, Hillsboro, OR (US); and Akira Mineji, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 23, 2021, as Appl. No. 17/408,985.
Application 17/408,985 is a division of application No. 16/548,918, filed on Aug. 23, 2019, granted, now 11,164,956.
Prior Publication US 2021/0384322 A1, Dec. 9, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66515 (2013.01) [H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 29/45 (2013.01); H01L 29/4983 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
etching a gate structure and a spacer relative to a top surface of a dielectric layer to form a recess, wherein a top surface of the spacer is etched to a first depth below the top surface of the dielectric layer and a top surface of the gate structure is etched to a second depth below the top surface of the spacer, and wherein the second depth is greater than the first depth;
forming a metal containing hard mask layer in the recess;
removing a portion of the dielectric layer to form a source/drain (S/D) contact opening; and
forming a S/D contact in the S/D contact opening, wherein a sidewall portion of the metal containing hard mask layer above the spacer is in contact with a sidewall portion of the S/D contact.