US 12,080,775 B2
Semiconductor device and forming method thereof
Wen-Kai Lin, Yilan County (TW); Shih-Chiang Chen, Taichung (TW); Po-Shao Lin, Taipei (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Hsinchu County (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,312.
Prior Publication US 2023/0062597 A1, Mar. 2, 2023
Int. Cl. H01L 29/76 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction, wherein each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures, and the composition of the outer region of each of the nanostructures includes oxide; and
a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures, wherein the gate structure comprises:
a plurality of high-k gate dielectric layers respectively surrounding the plurality of nano structures;
a work function layer surrounding each of the plurality of high-k gate dielectric layers; and
a fill metal layer surrounding the work function layer.