US 12,080,759 B2
Transistor source/drain regions and methods of forming the same
Yan-Ting Lin, Baoshan Township (TW); Wei-Jen Lai, Keelung (TW); Chien-I Kuo, Chiayi County (TW); Wei-Yuan Lu, Taipei (TW); Chia-Pin Lin, Xinpu Township (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 18, 2021, as Appl. No. 17/530,026.
Claims priority of provisional application 63/188,130, filed on May 13, 2021.
Prior Publication US 2022/0367622 A1, Nov. 17, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 21/823468 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
etching a source/drain recess in a nanostructure and a fin;
growing first epitaxial layers from a sidewall of the nanostructure and a top surface of the fin in the source/drain recess;
growing a second epitaxial layer from the first epitaxial layers with a growth process, the growth process having a first bottom-up growth rate from the first epitaxial layers and having a second bottom-up growth rate from the fin and the nanostructure, the first bottom-up growth rate less than the second bottom-up growth rate; and
growing a third epitaxial layer from the second epitaxial layer.