US 12,080,757 B2
Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices
Hao Cui, Santa Clara, CA (US); and Clifford Drowley, Santa Clara, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Sep. 22, 2023, as Appl. No. 18/371,956.
Application 18/085,985 is a division of application No. 17/350,237, filed on Jun. 17, 2021, granted, now 11,575,000, issued on Feb. 7, 2023.
Application 18/371,956 is a continuation of application No. 18/085,985, filed on Dec. 21, 2022, granted, now 11,824,086.
Claims priority of provisional application 63/040,853, filed on Jun. 18, 2020.
Prior Publication US 2024/0105767 A1, Mar. 28, 2024
Int. Cl. H01L 21/00 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01)
CPC H01L 29/0634 (2013.01) [H01L 29/66522 (2013.01); H01L 29/66734 (2013.01); H01L 29/66909 (2013.01); H01L 29/66924 (2013.01); H01L 29/7813 (2013.01); H01L 29/8083 (2013.01); H01L 21/02389 (2013.01); H01L 21/02458 (2013.01); H01L 21/02496 (2013.01); H01L 21/02502 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02642 (2013.01); H01L 21/28264 (2013.01); H01L 21/30617 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:
a III-nitride substrate having a first conductivity type;
a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches;
a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type;
a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;
a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;
a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer;
a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;
a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric;
and
a source metal layer coupled to an upper portion of the fourth III-nitride layer.