	US 12,080,755 B2
	Multi-layer polysilicon stack for semiconductor devices
Furen Lin, Chengdu (CN); Yunlong Liu, Chengdu (CN); Zhi Peng Feng, Chengdu (CN); Rui Liu, Chengdu (CN); Rui Song, Chengdu (CN); and Manoj K Jain, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 27, 2021, as Appl. No. 17/512,484.
Application 17/512,484 is a continuation of application No. PCT/CN2021/102341, filed on Jun. 25, 2021.
Prior Publication US 2022/0416014 A1, Dec. 29, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/495 (2006.01); H01L 27/08 (2006.01); H01L 29/66 (2006.01); H01L 49/02 (2006.01)

CPC H01L 28/91 (2013.01) [H01L 28/92 (2013.01)]

16 Claims

1. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a surface layer of a semiconductor substrate;

forming a first dielectric layer that lines a surface of the plurality of trenches;

forming a doped polysilicon layer on the first dielectric layer;

forming a second dielectric layer on the doped polysilicon layer;

forming an undoped polysilicon layer on the second dielectric layer;

removing the undoped polysilicon layer in regions of the surface layer lateral to the plurality of trenches, wherein the second dielectric layer in the regions of the surface layer is exposed as a result of removing the undoped polysilicon layer; and

removing a protective layer from a back side of the semiconductor substrate.