US 12,080,745 B2
Solid-state imaging device and electronic apparatus
Takatoshi Kameshima, Kanagawa (JP); Hideto Hashiguchi, Kanagawa (JP); Ikue Mitsuhashi, Kanagawa (JP); Hiroshi Horikoshi, Tokyo (JP); Reijiroh Shohji, Tokyo (JP); Minoru Ishida, Tokyo (JP); Tadashi Iijima, Kanagawa (JP); and Masaki Haneda, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jul. 25, 2022, as Appl. No. 17/814,651.
Application 17/814,651 is a continuation of application No. 16/495,335, granted, now 11,411,036, previously published as PCT/JP2018/011571, filed on Mar. 23, 2018.
Claims priority of application No. 2017-074805 (JP), filed on Apr. 4, 2017; and application No. 2017-130385 (JP), filed on Jul. 3, 2017.
Prior Publication US 2022/0359603 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); H01L 23/64 (2006.01); H01L 21/822 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 23/642 (2013.01); H01L 27/14634 (2013.01); H01L 21/8221 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A light detecting device, comprising:
a first substrate that includes a first semiconductor substrate and a first multi-layered wiring layer on the first semiconductor substrate, wherein the first semiconductor substrate has pixels;
a second substrate that includes a second semiconductor substrate, a second multi-layered wiring layer on a first side of the second semiconductor substrate, and an insulating layer on a second side of the second semiconductor substrate, wherein the second side of the second semiconductor substrate is opposite to the first side of the second semiconductor substrate;
a third substrate that includes a third semiconductor substrate and a third multi-layered wiring layer on the third semiconductor substrate, wherein
each of the second semiconductor substrate and the third semiconductor substrate includes a circuit,
the second substrate is between the first substrate and the third substrate,
the first multi-layered wiring layer is opposite to the second multi-layered wiring layer,
the insulating layer is opposite to the third multi-layered wiring layer,
the first substrate is electrically connected to the second substrate, and wherein
the insulating layer includes a first electrode,
the third multi-layered wiring layer includes a second electrode,
the second substrate includes a first bonding surface,
the third substrate includes a second bonding surface,
the first electrode is joined to the second electrode at the first bonding surface of the second substrate and the second bonding surface of the third substrate;
a first via that penetrates the second semiconductor substrate, wherein the first via electrically connects the first electrode to a first wiring in the second multi-layered wiring layer; and
a second via that electrically connects the second electrode to a second wiring in the third multi-layered wiring layer.