US 12,080,716 B2
Method of manufacturing semiconductor device
Takaaki Tsunomura, Tokyo (JP); Yoshiki Yamamoto, Tokyo (JP); Masaaki Shinohara, Tokyo (JP); Toshiaki Iwamatsu, Tokyo (JP); and Hidekazu Oda, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on May 15, 2023, as Appl. No. 18/317,500.
Application 18/317,500 is a continuation of application No. 16/928,542, filed on Jul. 14, 2020, granted, now 11,695,012.
Application 16/928,542 is a continuation of application No. 16/670,918, filed on Oct. 31, 2019, granted, now 10,756,115, issued on Aug. 25, 2020.
Application 16/670,918 is a continuation of application No. 15/695,410, filed on Sep. 5, 2017, granted, now 10,510,775, issued on Dec. 17, 2019.
Application 15/695,410 is a continuation of application No. 13/859,297, filed on Apr. 9, 2013, granted, now 9,935,125, issued on Apr. 3, 2018.
Claims priority of application No. 2012-088545 (JP), filed on Apr. 9, 2012.
Prior Publication US 2023/0282647 A1, Sep. 7, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 27/1207 (2013.01); H01L 29/66477 (2013.01); H01L 29/66628 (2013.01); H01L 29/66651 (2013.01); H01L 29/7834 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 29/41783 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate having:
a first region including a BOX (Buried Oxide) film formed on the semiconductor substrate, an SOI (Silicon On Insulator) layer formed on the first insulating film, a first gate insulating film formed on the SOI layer, a first gate electrode formed on the first gate insulating film, and a first hard mask formed on the first gate electrode, and
a second region including a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film, and a second hard mask formed on the second gate electrode;
(b) after the step of (a), forming a first insulating film so as to cover the SOI layer, a side surface of the first gate electrode, the first hard mask, the semiconductor substrate in the second region, a side surface of the second gate electrode and the second hard mask;
(c) after the step of (b), forming a second insulating film on the side surface of the first gate electrode via the first insulating film, and forming a third insulating film on the side surface of the second gate electrode via the first insulating film, a material of each of the second insulating film and the third insulating film being different from a material of the first insulating film, the material of the second insulating film being the same as the material of the third insulating film;
(d) after the step of (c), covering the third insulating film and the first insulating film, which is exposed from the third insulating film, in the second region with a resist film;
(e) after the step of (d), performing an etching process in a state that the third insulating film and the first insulating film, which is exposed from the third insulating film, in the second region is covered with the resist film, thereby removing a portion, which is exposed from the second insulating film, of the first insulating film in the first region;
(f) after the step of (e), forming an epitaxial layer on the SOI layer exposed from the first insulating film by performing the step of (e);
(g) after the step of (f), removing a portion, which is exposed from the third insulating film, of the first insulating film in the second region in a state that a portion of the first insulating film located between the first gate electrode and the second insulating film is exposed;
(h) after the step of (g), removing the second insulating film;
(i) after the step of (h), implanting a first impurity into the SOI layer, thereby forming a first extension region in the SOI layer; and
(j) after the step of (i), forming a fourth insulating film on the side surface of the first gate electrode via the first insulating film such that the fourth insulating film is in contact with a portion, which is exposed from the first insulating film in the first region, of the side surface of the first gate electrode, a material of the fourth insulating film being the same as the material of the second insulating film.