US 12,080,715 B2
Semiconductor device with varying gate dimensions and methods of forming the same
Guan-Wei Huang, Hsinchu (TW); Yu-Shan Lu, Zhubei (TW); Yu-Bey Wu, Hsinchu (TW); Jiun-Ming Kuo, Taipei (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 20, 2021, as Appl. No. 17/407,566.
Prior Publication US 2023/0054372 A1, Feb. 23, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/82385 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first semiconductor fin disposed over a substrate;
a second semiconductor fin disposed over the substrate and adjacent to the first semiconductor fin;
a metal gate stack disposed over the substrate,
wherein the metal gate stack includes a first region, a second region, and a third region,
wherein the first region is disposed over the first semiconductor fin, the second region is disposed over the second semiconductor fin, and the third region connects the first region to the second region in a continuous profile, and, wherein, the third region has a profile defined by an inverted trapezoid when viewed in a top view, and
wherein the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length; and
source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack.