US 12,080,711 B2
Induced super-junction transistors
John Lin, Carlsbad, CA (US); and Jinbiao Huang, Nashua, NH (US)
Assigned to NuVolta Technologies (Hefei) Co., Ltd., Hefei (CN)
Appl. No. 17/623,531
Filed by NuVolta Technologies (Hefei) Co., Ltd., Hefei (CN)
PCT Filed Dec. 13, 2021, PCT No. PCT/CN2021/137504
§ 371(c)(1), (2) Date Dec. 28, 2021,
PCT Pub. No. WO2022/143125, PCT Pub. Date Jul. 7, 2022.
Claims priority of provisional application 63/131,658, filed on Dec. 29, 2020.
Prior Publication US 2023/0253402 A1, Aug. 10, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/8236 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0883 (2013.01) [H01L 21/26513 (2013.01); H01L 21/8236 (2013.01); H01L 29/0653 (2013.01); H01L 29/1095 (2013.01); H01L 29/4238 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first drain/source region and a second drain/source region over a substrate;
a first gate adjacent to the first drain/source region, the first gate comprising a plurality of first fingers forming a first comb structure; and
a second gate adjacent to the second drain/source region, the second gate comprising a plurality of second fingers forming a second comb structure, wherein the plurality of first fingers and the plurality of second fingers are placed in an alternating manner, and wherein the first drain/source region, the second drain/source region, the first gate and the second gate form two back-to-back connected transistors.