US 12,080,707 B2
Semiconductor device
Tatsuya Naito, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Jul. 18, 2023, as Appl. No. 18/353,907.
Application 17/172,090 is a division of application No. 15/900,810, filed on Feb. 21, 2018, granted, now 10,930,647, issued on Feb. 23, 2021.
Application 18/353,907 is a continuation of application No. 17/887,504, filed on Aug. 14, 2022, granted, now 11,735,584.
Application 17/887,504 is a continuation of application No. 17/172,090, filed on Feb. 10, 2021, granted, now 11,430,784, issued on Aug. 30, 2022.
Application 15/900,810 is a continuation of application No. PCT/JP2017/009843, filed on Mar. 10, 2017.
Claims priority of application No. 2016-047188 (JP), filed on Mar. 10, 2016; application No. 2016-201972 (JP), filed on Oct. 13, 2016; and application No. 2017-024925 (JP), filed on Feb. 14, 2017.
Prior Publication US 2023/0361111 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/32 (2006.01); H01L 29/36 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01)
CPC H01L 27/0635 (2013.01) [H01L 21/76 (2013.01); H01L 21/765 (2013.01); H01L 27/0727 (2013.01); H01L 29/0696 (2013.01); H01L 29/0834 (2013.01); H01L 29/1095 (2013.01); H01L 29/32 (2013.01); H01L 29/36 (2013.01); H01L 29/404 (2013.01); H01L 29/405 (2013.01); H01L 29/407 (2013.01); H01L 29/4238 (2013.01); H01L 29/739 (2013.01); H01L 29/7397 (2013.01); H01L 29/78 (2013.01); H01L 29/8613 (2013.01); H01L 29/8611 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate having a drift region of a first conductivity type and a base region of a second conductivity type provided above the drift region;
a plurality of trench portions that are formed at an upper surface of the semiconductor substrate and arrayed parallel to one another, each of the plurality of trench portions penetrating the base region; and
a plurality of mesa portions formed between respective trench portions, wherein among the plurality of mesa portions, at least one mesa portion includes:
a first semiconductor region of the first conductivity type having a concentration higher than a concentration of the drift region;
a second semiconductor region of the second conductivity type having a concentration higher than a concentration of the base region; and
an accumulation region of the first conductivity type that is formed between the base region and the drift region and has a concentration higher than the concentration of the drift region,
the drift region does not extend above the accumulation region,
in a longitudinal direction of the plurality of trench portions, the accumulation region is formed to extend beyond an end portion of the first semiconductor region, and
the semiconductor device further comprising:
a diode portion including a cathode region of the first conductivity type formed at a lower surface of the semiconductor substrate;
a transistor portion including a collector region of the second conductivity type formed at the lower surface of the semiconductor substrate; and
one or more boundary mesa portions that (i) is formed between (a) a boundary between the transistor portion and the diode portion and (b) a mesa portion, among the at least one mesa portion, that is on a side of the transistor portion relative to the boundary and includes the first semiconductor region closest to the boundary and (ii) does not include the first semiconductor region.