US 12,080,703 B2
Semiconductor cell blocks having non-integer multiple of cell heights
Vassilios Gerousis, Liberty Hill, TX (US); Rwik Sengupta, Leander, TX (US); Joon Goo Hong, Austin, TX (US); Kevin Traynor, Livingston, TX (US); Tanya Abaya, Austin, TX (US); Dharmendar Palle, Austin, TX (US); and Mark S. Rodder, Dallas, TX (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 20, 2022, as Appl. No. 18/048,186.
Application 18/048,186 is a division of application No. 16/853,535, filed on Apr. 20, 2020, granted, now 11,552,067.
Claims priority of provisional application 62/979,080, filed on Feb. 20, 2020.
Prior Publication US 2023/0104185 A1, Apr. 6, 2023
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 23/528 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); H01L 23/5286 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor cell block comprising:
a plurality of layers arranged in a stack, the plurality of layers comprising one or more first layers each having a first height and one or more second layers each having a second height, wherein the second height is larger than the first height, and wherein the second height is a non-integer multiple of the first height;
a first semiconductor logic cell having a first cell height in one of the plurality of layers;
a second semiconductor logic cell having a second cell height in one of the plurality of layers, wherein the second cell height is larger than the first cell height, and wherein the second cell height is a non-integer value multiple of the first cell height; and
at least one power rail coupled to the first and second semiconductor logic cells, wherein the first cell height and the second cell height are defined in a vertical direction perpendicular to a plane in which the at least one power rail extends.