| CPC H01L 25/18 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
a redistribution structure;
a ground bump and a signal bump on a lower surface of the redistribution structure;
a frame on an upper surface of the redistribution structure, the frame including a ground connection pattern electrically connected to the ground bump and a signal connection pattern electrically connected to the signal bump;
an application processor (AP) chip inside a hole configured to pass through the frame;
a molding on the upper surface of the redistribution structure, the molding covering the AP chip and the frame;
a conductive layer on the molding;
an upper insulating layer on the conductive layer;
a first opening passing through the upper insulating layer and exposing an upper surface of the conductive layer;
a second opening overlapping the first opening in a top view, the second opening passing through the conductive layer and exposing the ground connection pattern; and
a third opening passing through the upper insulating layer and exposing the signal connection pattern.
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