| CPC H01L 25/18 (2013.01) [H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
an interposer substrate;
an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate;
a chip stack on a bottom surface of the interposer substrate, the chip stack including a plurality of stacked lower semiconductor chips, each of the lower semiconductor chips including a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate;
a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip; and
a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias,
wherein the upper semiconductor chip is electrically connected through the interposer substrate to the through vias, and
wherein the interposer substrate has a larger area than the top surface of the chip stack from a plan view.
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