US 12,080,678 B2
Methods and systems for manufacturing semiconductor devices
Wei Zhou, Boise, ID (US); Bret K. Street, Meridian, ID (US); Benjamin L. McClain, Boise, ID (US); and Mark E. Tuttle, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,572.
Application 17/099,625 is a division of application No. 16/236,257, filed on Dec. 28, 2018, granted, now 10,840,210, issued on Nov. 17, 2020.
Application 17/881,572 is a continuation of application No. 17/099,625, filed on Nov. 16, 2020, granted, now 11,410,962.
Prior Publication US 2023/0197669 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 24/75 (2013.01) [H01L 23/481 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 2224/75317 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/95091 (2013.01)] 11 Claims
OG exemplary drawing
 
7. A semiconductor bonding apparatus comprising:
a first stage of a having a first pressing surface;
a second stage having a second pressing surface facing the first pressing surface;
a stopper wall at least partially surrounding a cavity configured to a stack of semiconductor dies, and wherein the stopper wall has a stopper height measured from the second pressing surface in a direction normal to the first pressing surface and configured to stop a relative movement of the first and second pressing surfaces toward each other at a distance less than or equal to the stopper height.