US 12,080,665 B2
Memory devices having vertical transistors and methods for forming the same
Hongbin Zhu, Wuhan (CN); Wei Liu, Wuhan (CN); Yanhong Wang, Wuhan (CN); and Ning Jiang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 16, 2021, as Appl. No. 17/553,781.
Application 17/553,781 is a continuation of application No. PCT/CN2021/115820, filed on Aug. 31, 2021.
Prior Publication US 2023/0060149 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor; and
a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction,
wherein the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction; and
a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction; and
a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface.