| CPC H01L 24/06 (2013.01) [H01L 24/08 (2013.01); H01L 25/0655 (2013.01); H01L 29/7813 (2013.01); H01L 2224/06152 (2013.01); H01L 2224/08225 (2013.01)] | 11 Claims |
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1. A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:
a semiconductor layer;
a metal layer in contact with a rear surface of the semiconductor layer;
a first vertical MOS transistor in a first internal region inside the semiconductor layer;
a second vertical MOS transistor in a second internal region inside the semiconductor layer, the second internal region contacting the first internal region at an internal boundary line in a plan view of the semiconductor layer;
a plurality of first source pads and a first gate pad in a first upper surface region of an upper surface of the semiconductor layer, the plurality of first source pads being connected to a source electrode of the first vertical MOS transistor, the first gate pad being connected to a gate electrode of the first vertical MOS transistor; and
a plurality of second source pads and a second gate pad in a second upper surface region of the upper surface of the semiconductor layer, the plurality of second source pads being connected to a source electrode of the second vertical MOS transistor, the second gate pad being connected to a gate electrode of the second vertical MOS transistor, the second upper surface region being adjacent to the first upper surface region in the plan view of the semiconductor layer, wherein:
in the plan view of the semiconductor layer, the first internal region and the second internal region divide the semiconductor layer into two equal parts in terms of surface area,
in the plan view of the semiconductor layer, the first upper surface region and the second upper surface region divide the semiconductor layer into two equal parts in terms of surface area,
the semiconductor layer includes a semiconductor substrate,
the semiconductor substrate functions as a common drain region for the first vertical MOS transistor and the second vertical MOS transistor,
the semiconductor layer has a rectangular plan view shape,
in the plan view of the semiconductor layer, the internal boundary line monotonically changes in a first direction in which a first side of the semiconductor layer extends and a second direction in which a second side of the semiconductor layer orthogonal to the first side extends,
in the plan view of the semiconductor layer, the internal boundary line has two terminal ends, a first terminal end and a second terminal end, and an acute angle between an extension of a virtual straight line connecting the first terminal end and the second terminal end and an extension of a side of the semiconductor layer at which neither the first terminal end nor the second terminal end terminates is greater than or equal to 16 degrees, and
in the plan view of the semiconductor layer, the internal boundary line is limited to where an active region of the first vertical MOS transistor and an active region of the second vertical MOS transistor face each other.
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