| CPC H01L 24/05 (2013.01) [H01L 21/561 (2013.01); H01L 24/13 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/18162 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first semiconductor chip and a second semiconductor chip adjacent to each other in a first direction,
the first semiconductor chip comprising,
a first substrate having a first front surface and a first rear surface opposite to each other;
first interconnections on the first front surface of the first substrate;
a first interlayer insulating layer covering the first interconnections;
a first pad and first wirings on the first interlayer insulating layer, and electrically connected to the first interconnections;
a first protective insulating layer covering the first pad and the first wirings and having a first opening exposing a portion of the first pad;
a first bump on the first protective insulating layer and electrically connected to the first pad;
a first protruding electrode on the first rear surface of the first substrate; and
a first through electrode extending in the first substrate in the first direction and electrically connecting the first protruding electrode and the first interconnections to each other,
the second semiconductor chip comprising,
a second substrate having a second front surface and a second rear surface opposite to each other;
second interconnections on the second front surface of the second substrate;
a second interlayer insulating layer covering the second interconnections;
a second pad and second wirings on the second interlayer insulating layer, and electrically connected to the second interconnections;
a second protective insulating layer covering the second pad and the second wirings and having a second opening exposing a portion of the second pad; and
a second bump on the second protective insulating layer and including a pillar structure electrically connected to the second pad and a solder connecting the pillar structure and the first protruding electrode,
wherein a thickness of the second pad in the first direction is greater than a thickness of each of the second interconnections in the first direction,
wherein a width of a gap between the second pad and the second wirings adjacent to each other in a second direction, perpendicular to the first direction, is greater than or equal to the thickness of the second pad in the first direction,
wherein the pillar structure has a first side having a convex portion within the second opening of the second protective insulating layer, and a second side having a concave portion aligned with the convex portion in the first direction, wherein the second side is in contact with the solder of the second bump,
wherein the first protruding electrode has a third side in contact with the solder of the second bump and substantially flat,
wherein the second protective insulating layer includes a first protective layer on the second pad and the second wirings, a second protective layer on the first protective layer, and a third protective layer on the second protective layer, and
wherein the second opening of the second protective insulating layer has a narrow region penetrating through the first and second protective layers, and a wide region penetrating through the third protective layer and exposing a portion of the second protective layer in the first direction.
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