US 12,080,654 B2
Flexible circuit board and chip package including same
Jun Young Lim, Seoul (KR); Hyung Kyu Yoon, Seoul (KR); and Sung Min Chae, Seoul (KR)
Assigned to LG INNOTEK CO., LTD., Seoul (KR)
Filed by LG INNOTEK CO., LTD., Seoul (KR)
Filed on May 15, 2023, as Appl. No. 18/197,245.
Application 18/197,245 is a continuation of application No. 17/559,125, filed on Dec. 22, 2021, granted, now 11,694,964.
Application 17/559,125 is a continuation of application No. 16/756,552, granted, now 11,239,172, issued on Feb. 1, 2022, previously published as PCT/KR2018/012687, filed on Oct. 25, 2018.
Claims priority of application No. 10-2017-0145443 (KR), filed on Nov. 2, 2017.
Prior Publication US 2023/0282590 A1, Sep. 7, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/5387 (2013.01) [H01L 23/49866 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flexible circuit board comprising:
a substrate;
a first conductive pattern part disposed under a first surface of the substrate;
a second conductive pattern part and a first dummy pattern part disposed over a second surface opposite to the first surface of the substrate;
a first protection layer disposed under the first conductive pattern part; and
a second protection layer disposed over the second conductive pattern part and the first dummy pattern part,
wherein the first dummy pattern part is vertically overlapped with the first conductive pattern part disposed at an outermost periphery of the substrate, the first protective layer and the second protective layer, and
wherein the first conductive pattern part includes:
a first wiring pattern layer, and
a first plating layer disposed under the first wiring pattern layer and including tin (Sn);
wherein the first dummy pattern part includes:
a second wiring pattern layer, and
a second plating layer disposed over the second wiring pattern layer and including tin (Sn),
wherein a thickness of the second plating layer of the first dummy pattern part under the second protective layer is different from a thickness of the first plating layer of the first conductive pattern part over the first protective layer.