US 12,080,653 B2
Formation method of chip package with fan-out structure
Shing-Chao Chen, Zhubei (TW); Chih-Wei Lin, Zhubei (TW); Tsung-Hsien Chiang, Hsinchu (TW); Ming-Da Cheng, Taoyuan (TW); and Ching-Hua Hsieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 24, 2021, as Appl. No. 17/328,925.
Application 16/222,047 is a division of application No. 15/292,762, filed on Oct. 13, 2016, granted, now 10,157,846, issued on Dec. 18, 2018.
Application 17/328,925 is a continuation of application No. 16/725,352, filed on Dec. 23, 2019, granted, now 11,404,381.
Application 16/725,352 is a continuation of application No. 16/222,047, filed on Dec. 17, 2018, granted, now 10,515,900, issued on Dec. 24, 2019.
Prior Publication US 2021/0280520 A1, Sep. 9, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/566 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/18 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0657 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1431 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a chip package, comprising:
disposing a semiconductor die over a carrier substrate;
forming a protection layer over the carrier substrate to surround the semiconductor die;
forming a dielectric layer over the protection layer and the semiconductor die after the protection layer is formed;
planarizing a first portion of the dielectric layer;
planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized;
forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized, wherein the conductive layer has a plurality of first protruding portions extending into the dielectric layer; and
forming a second dielectric layer over the dielectric layer and the conductive layer, wherein the second dielectric layer has a plurality of second protruding portions extending into the dielectric layer, and each of the first protruding portions and the second protruding portions is thinner than the dielectric layer.